The invention is directed to an adder cell for constructing a carry-save adder.
A carry-save adder is known from the book "Computer Arithmetic" by K. Hwang, John Wiley and Sons, New York, 1979, pages 98 through 103 particularly FIG. 4.1 and FIG. 4.2. Every first adder cell has three inputs, each of which receives equivalent bits of three binary numbers to be added to one another. The carry-save adder of FIG. 4.1 is composed of n adder cells that are also referred to as a full adder. The carry output of every adder cell is intermediately stored in a carry-save register and is supplied to the next higher adder cell. A combination between a carry-save and carry-propagate adder, by contrast, is shown in FIG. 4.2. The sum outputs of the first carry-save adder cells are conducted to first inputs of the carry-propagate adder; the carry outputs of the first adder cells (with the exception of the most significant adder cell) are linked via carry-save registers to second inputs of the carry-propagate adder. A sum word resulting from the addition appears at the outputs of the carry-propagate adder. Differing from an adder arrangement using the carry-propagate principle, the carries of all first adder cells, in an addition to three binary numbers, are simultaneously formed and, in addition to the intermediate sum word taken at the first adder cells, are available as a carry word. An adder constructed in this fashion functions according to the "carry-save" principal.
In conventional adder cells, the sum running time is usually considerably longer than the carry running time. The reason for this difference is that the sum signal must traverse a greater number of logical gates. These different running times are rather meaningful given "carry-propagate" adders such as, for example, the "carry-ripple" adder because the carry signal must traverse many stages, while the sum signal traverses only one stage. However, the situation is different for "carry-save" adders, in which the sum signal and the carry signal are separately forwarded to arbitrary inputs of following adders. It is advantageous that the sum signal and carry signal be formed with identical speed, insofar as possible.